Human Summary

This PR brings the following optimizations to AICPU kernel initialization:

• The orchestrator thread does not take part in (or waits for) AI core handshaking. It goes straight into creating the task graph
• The scheduler threads only handshake (as a batch) the AI cores that they manage.
• Initialization barriers are removed. Once the scheduler threads are done handshaking, they can start working, regardless of what the other scheduler threads are doing.

This optimization improves only the fixed-cost of initialization so it yields higher gains on small kernels. On larger kernels, the gains are diluted out per Amdahl's Law.

Update — a5 port + fixes

Since the original a2a3-only draft:

• Ported to a5 (src/a5/.../tensormap_and_ringbuffer) — same restructure. a5 shares the 1:2 blocked layout but has RUNTIME_MAX_WORKER=108 (36 AIC + 72 AIV) vs a2a3's 72; every count derives from cores_total_num_, so the port is count-agnostic. assign_own_clusters mirrors each arch's own post_handshake_init: the a2a3 variant also does the AsyncCtx constant-prefill / slab-clear, while a5 does sub_block_id only (a5 writes AsyncCtx per-dispatch in build_payload).
• Divisibility guard — pre_handshake_init now fails fast when cores_total_num_ % 3 != 0 instead of silently leaving the tail AIV cores in no cluster (which would hang at the op-execute timeout). Holds for the serial path too.
• Comment cleanup — dropped the [SPIKE …] planning tags and rewrote the change-narration comments per the repo's comment rules.
• CI/lint — fixed clang-format (short-loop) and markdownlint (MD040 fenced-block language, MD060 table alignment) so pre-commit is green.

Verification: a2a3sim (33) + a5sim (26) tensormap_and_ringbuffer suites green; all required CI checks pass, including st-onboard-a2a3 and st-onboard-a5 on real silicon — the a5 onboard run confirms the blocked [0,N/3) AIC / [N/3,N) AIV handshake-enumeration assumption holds on a5 hardware.

⚠️ Measured on the current base (48d92e8), a2a3 onboard, 100 rounds/case: the isolated init/preamble saving is a fixed ~11 µs/run, consistent across 8 workloads regardless of size (the device_wall − effective gap drops 10–12 µs in every case; the larger device_wall swings are orch/sched compute run-to-run variance this PR does not touch). The ~63 µs / −25% numbers in the AI Writeup below are against an older pre-#1310 baseline whose preamble was still ~200 µs — today's main has already cut that, so the removable barrier + leader post_handshake_init is worth ~11 µs. Still real and size-independent (so it helps high-frequency per-op dispatch), just an order of magnitude smaller than the original headline.

AI Writeup

tl;dr for humans

Every AICPU run, the scheduler init still puts an all-thread barrier around
the AICore handshake: all threads greet the 72 cores, then the leader serially
builds the core→thread assignment and prefills every core's dispatch payload,
before any thread starts working. This PR removes that barrier. Each scheduler
thread greets only the cores it will dispatch to (computable up front from
the fixed, blocked 1 AIC : 2 AIV layout), self-assigns them, and starts
dispatching to its own cores as soon as they're up — no waiting for peers, no
leader-serialized setup. The orchestrator thread likewise skips the handshake
and starts building the graph immediately.

Net: ~63 µs of per-run scheduler init removed, entirely in the preamble, by
parallelizing the handshake + core assignment across the threads that own the
cores. The effect scales inversely with run size — a big win on small /
per-op workloads, and neutral (never a regression) on whole-model
decode/prefill where the fixed cost amortizes.

What changes

1. Orchestrator decouple. The orchestrator (tidx == nthreads-1) doesn't
   dispatch to cores, so it skips the handshake and returns to run() to build
   the graph immediately, deriving AIC/AIV counts from the fixed 1:2 ratio.
2. Barrier-free per-thread scheduler init. Each scheduler thread handshakes
   only its owned clusters (ci = {ci, N/3+2ci, N/3+2ci+1}, owned by ci % active_sched_threads_) via handshake_owned_clusters (batched 4-phase
   protocol, 2 barriers) and self-assigns them via assign_own_clusters — no
   all-thread barrier, no leader-serialized post_handshake_init. pre_handshake _init derives the counts + resets the run counters. DFX builds keep a
   profiling-only barrier (pmu needs all physical_core_ids_); serial /
   single-thread fall back to the original path.

Why it's safe: the blocked [AIC…][AIV…] layout and 1:2 ratio are
compile-time-and-hardware-enforced invariants (identical on sim + onboard), so
each thread's owned cluster set is exact and known before the handshake.

Mechanism

The saving is entirely in the preamble phase. hc_post, strace_timing --tree, this PR vs baseline:

A/B benchmark — 37 single-die pypto-lib workloads, 20 rounds

.so-swap A/B, this PR vs the pre-change baseline, default config,
device_wall median over 20 rounds, devices 2–5 (unlocked, verified-idle),
a2a3 / Ascend 910B2. 35/37 faster, zero regressions.

By size (the ~63 µs is a fixed per-run cost, so % impact ≈ 63 µs / run):

Reading the numbers — single-round vs amortized

These harnesses run one round per process, so device_wall includes the
per-run scheduler init. That's why standalone component kernels show large wins
while whole-model runs (decode_tq 40L −0.1%, prefill_tq_draft +0.1%) are
neutral — the ~63 µs amortizes across a 120–470 ms forward. For reference, the
in-repo scene test benchmark_bgemm (100 rounds in one warm process, init
amortized) shows ~−0.7%. So end-to-end impact depends on serving
granularity: per-op / per-layer dispatch pays the init each time (large win);
whole-model-per-step amortizes it (neutral, never a regression).

Correctness

Golden PASS on the current base: benchmark_bgemm, alternating_matmul_add,
batch_paged_attention, qwen3_14b_decode; decode_tq 4L/8L complete +
validate. Zero regressions across the 37-workload × 20-round sweep above.

Scope / follow-ups

• a5 sim-verified, onboard pending — the port passes a5sim golden, but the
  self-assign path assumes the AICore handshake reports cores in blocked
  [0,N/3) AIC / [N/3,N) AIV order; no a5 doc guarantees that enumeration, so
  run a5 onboard golden before relying on it.
• Confirm the target serving path's dispatch granularity (per-layer / per-op vs
  whole-model) to know the end-to-end impact.
• The barrier-free handshake-failure path (abort_and_shutdown) is documented
  as bounded/best-effort: a peer past run()'s is_completed() gate isn't
  joined, but its own cores are valid and the host device reset that follows a
  handshake failure reaps every core. Still not race-free, and
  emergency_shutdown isn't exercised by golden (the invalid-physical_core_id
  trigger needs a hw/sim fault-injection hook the UT harness lacks).
• On the decoupled path, handshake_partition / post_handshake_init /
  assign_cores_to_threads now serve only the serial/single-thread fallback +
  the DFX barrier — keep or prune with the fallback's fate.